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Buscar por Autor Jimborean, Alexandra

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2014_IJPP_Alexandra_Jimborean.pdf.jpg9-ago-2013-Dynamic and Speculative Polyhedral ParallelizationUsing Compiler-Generated Skeletons
aros-ipdps15.pdf.jpg25-may-2015-A Dual-Consistency Cache Coherence Protocol
2016_TPDS_Alberto_Ros_author.pdf.jpg2016-A hybrid static-dynamic classification for dual-consistency cache coherence
2016_CC_Konstantinos_Koukos.pdf.jpg17-mar-2016-Multiversioned Decoupled Access-Execute: the Key to Energy-Efficient Compilation of General-Purpose Programs
2018_TPDS_Alexandra_Jimborean_author.pdf.jpg2018-Automatic Detection of Large Extended Data-Race-Free Regions with Conflict Isolation
2018_TC_Kim_Anh_Tran.pdf.jpg1-abr-2018-Static Instruction Scheduling for High Performance on Limited Hardware
SWOOP.pdf.jpg11-jun-2018-SWOOP: Software-Hardware Co-design for Non-speculative, Execute-Ahead, In-Order Cores
Understanding Selective Delay as a Method.pdf.jpg2020-Understanding Selective Delay as a Method for Efficient Secure Speculative Execution
aros-ipc20.pdf.jpgmay-2020-The Entangling Instruction Prefetcher
aros-cal20.pdf.jpgjun-2020-The Entangling Instruction Prefetcher
ktran-pact20.pdf.jpgoct-2020-Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design
ssingh-pact20.pdf.jpgoct-2020-Regional Out-of-Order Writes in Total Store Order
2012_CC_Alexandra_Jimborean_HAL.pdf.jpgfeb-2021-VMAD: a virtual machine for advanced dynamic. Analysis of programs
mshimchenko-supe21.pdf.jpgjun-2021-Analysing Software Prefetching Opportunities in Hardware Transactional Memory
aros-isca21.pdf.jpgjun-2021-A Cost-Effective Entangling Prefetcher for Instructions
jcebrian-tpds22.pdf.jpgabr-2022-Compiler-Assisted Compaction/Restoration of SIMD Instructions
gchacon-iccd22.pdf.jpgoct-2022oct-2022Composite Instruction Prefetching
ssingh-micro22.pdf.jpg18-dic-2023-Exploring Instruction Fusion Opportunities in General Purpose Processors
aros-tc24.pdf.jpg2024-Wrong-Path-Aware Entangling Instruction Prefetcher
CELLO Compiler Assisted Efficient.pdf.jpg-2023CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions
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