Por favor, use este identificador para citar o enlazar este ítem: https://doi.org/10.1109/ICCD56317.2022.00076

Título: Composite Instruction Prefetching
Fecha de publicación: oct-2022
Fecha de defensa / creación: oct-2022
Editorial: IEEE Computer Society
Cita bibliográfica: 40th IEEE International Conference on Computer Design (ICCD)
ISSN: 1063-6404
ISBN: 978-1-6654-6187-0
Palabras clave: Instruction prefetching
First-level caches
Datacenter applications
Hardware prefetching
Hnstruction caches
Resumen: Prefetching is a pivotal mechanism for effectively masking latencies due to the processor/memory performance gap. Instruction prefetchers prevent costly instruction fetch stalls by requesting blocks of instruction memory in advance of their use to keep the pipeline front-end busy. the rapidly increasing instruction footprints of modern workloads have amplified the importance of such research. We propose a framework to leverage the complementary prefetching behaviors of existing prefetching techniques to create composite prefetchers. We show that recently proposed instruction prefetching techniques leverage different mechanisms from one another and find that in many cases, different prefetchers are complementary to each other. Composite prefetching allows for higher performance at lower storage overheads by combining the coverage of different complex prefetchers. We demonstrate a framework for selecting and combining state-of-the-art complex prefetchers, in a ”plug-and-play” fashion, to identify the best performing combinations at various hardware overheads. We show that for every storage capacity constraint analyzed, composite prefetching outperforms prior prefetching schemes with greater improvements shown at smaller capacity constraints.
Autor/es principal/es: Chacon, Gino
Garza, Elba
Jimborean, Alexandra
Ros, Alberto
Gratz, Paul
Jimenez, Daniel
Mirbagher-Ajorpaz, Samira
Facultad/Departamentos/Servicios: Facultades, Departamentos, Servicios y Escuelas::Departamentos de la UMU::Ingeniería y Tecnología de Computadores
Forma parte de: International Conference on Computer Design (ICCD)
URI: http://hdl.handle.net/10201/132445
DOI: https://doi.org/10.1109/ICCD56317.2022.00076
Tipo de documento: info:eu-repo/semantics/article
Número páginas / Extensión: 8
Derechos: info:eu-repo/semantics/openAccess
Atribución 4.0 Internacional
Attribution-NonCommercial-NoDerivatives 4.0 Internacional
Descripción: © 2022. The authors. This document is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0 This document is the accepted version of a published work that appeared in final form in 40th IEEE International Conference on Computer Design (ICCD). To access the final work, see DOI: https://doi.org/10.1109/ICCD56317.2022.00076
Aparece en las colecciones:Artículos: Ingeniería y Tecnología de Computadores

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