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https://doi.org/10.1109/MICRO56248.2022.00026
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Título: | Exploring Instruction Fusion Opportunities in General Purpose Processors |
Fecha de publicación: | 18-dic-2023 |
Editorial: | IEEE Press |
Cita bibliográfica: | MICRO '22: Proceedings of the 55th Annual IEEE/ACM International Symposium on MicroarchitectureOctober 2022 Pages 199–212 |
ISBN: | 978-1-6654-6272-3 |
Palabras clave: | General purpose processors Microarchitecture Instruction fusion |
Resumen: | The Complex Instruction Set Computer (CISC) paradigm has led to the introduction of instruction cracking in which an architectural instruction is divided into multiple microarchitectural instructions (μ-ops). However, the dual concept, instruction fusion is also prevalent in modern microarchitectures to maximize resource utilization. In essence, some architectural instructions are too complex to be executed as a unit, so they should be cracked, while others are too simple to waste resources on executing them as a unit, so they should be fused with others. In this paper, we focus on instruction fusion and explore opportunities for fusing additional instructions in a high- performance general purpose pipeline. We show that enabling fusion for common RISC-V idioms improves performance by 7%. Then, we determine experimentally that enabling fusion only for memory instructions achieves 86% of the potential of fusion in this particular case. Finally, we propose the Helios microarchitecture, able to fuse non-consecutive and non-contiguous memory instructions, and discuss microarchitectural changes required to do so efficiently while preserving correctness. Helios allows to fuse an additional 5.5% of dynamic instructions, yielding a 14.2% performance uplift over no fusion (8.2% over baseline fusion). |
Autor/es principal/es: | Singh, Sawan Perais, Arthur Jimborean, Alexandra Ros, Alberto |
Facultad/Departamentos/Servicios: | Facultades, Departamentos, Servicios y Escuelas::Departamentos de la UMU::Ingeniería de la Información y las Comunicaciones |
Forma parte de: | 55th International Symposium on Microarchitecture (MICRO) |
URI: | http://hdl.handle.net/10201/124785 |
DOI: | https://doi.org/10.1109/MICRO56248.2022.00026 |
Tipo de documento: | info:eu-repo/semantics/article |
Número páginas / Extensión: | 14 |
Derechos: | info:eu-repo/semantics/openAccess Atribución 4.0 Internacional Attribution-NonCommercial-NoDerivatives 4.0 Internacional |
Descripción: | © 2023. IEEE. This document is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0 This document is the accepted version of a published work that appeared in final form in MICRO '22: Proceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture To access the final work, see DOI: https://doi.org/10.1109/MICRO56248.2022.00026 |
Aparece en las colecciones: | Artículos: Ingeniería y Tecnología de Computadores |
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