Por favor, use este identificador para citar o enlazar este ítem: https://doi.org/10.1007/s11227-021-03897-z

Título: Analysing Software Prefetching Opportunities in Hardware Transactional Memory
Fecha de publicación: jun-2021
Cita bibliográfica: Journal of Supercomputing, published 02 June 2021
Palabras clave: Hardware Transactional Memory
Parallel programming
Software prefetching
Resumen: Hardware Transactional Memory emerged to make parallel programming more accessible. However, the performance pitfall of this technique is squashing speculatively executed instructions and re-executing them in case of aborts, ultimately resorting to serialization in case of repeated conflicts. A significant fraction of aborts occur due to conflicts (concurrent reads and writes to the same memory location performed by different threads). Our proposal aims to reduce conflict aborts by reducing the window of time during which transactional regions can suffer conflicts. We achieve this by using software prefetching instructions inserted automatically at compile-time. Through these prefetch instructions, we intend to bring the necessary data for each transaction from the main memory to the cache before the transaction itself starts to execute, thus converting the otherwise long latency cache misses into hits during the execution of the transaction. The obtained results show that our approach decreases the number of aborts by 30% on average and improves performance by up to 19% and 10% for two out of the eight evaluated benchmarks. We provide insights into when our technique is beneficial given certain characteristics of the transactional regions, the advantages and disadvantages of our approach, and finally, discuss potential solutions to overcome some of its limitations.
Autor/es principal/es: Shimchenko, Marina
Titos-Gil, Rubén
Fernández-Pascual, Ricardo
Acacio Sánchez, Manuel Eugenio
Kaxiras, Stefanos
Ros, Alberto
Jimborean, Alexandra
Facultad/Departamentos/Servicios: Facultades, Departamentos, Servicios y Escuelas::Departamentos de la UMU::Ingeniería y Tecnología de Computadores
URI: http://hdl.handle.net/10201/114644
DOI: https://doi.org/10.1007/s11227-021-03897-z
Tipo de documento: info:eu-repo/semantics/article
Número páginas / Extensión: 27
Derechos: info:eu-repo/semantics/openAccess
Atribución 4.0 Internacional
Aparece en las colecciones:Artículos: Ingeniería y Tecnología de Computadores

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