Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10201/114664

Título: BL∪E: A Timely, IP-based Data Prefetcher
Fecha de publicación: jun-2021
Palabras clave: Data prefetcher
Last level cache
Timely
Resumen: High-performance prefetchers require not only predicting the future cache lines that will be requested but also when they will be requested. Timeliness is therefore an essential property for getting the maximum performance from a prefetcher. Bringing the cache line too early to cache can decrease the coverage of the prefetcher when such cache line is evicted before is requested. On the other hand, prefetching the data too late can lead to late prefetchers, and thus, sub-optimal performance. This paper presents BL∪E, a data prefetcher that predicts the prefetched cache lines based on timeliness. The prefetcher accounts for the time required to fetch a cache line and issues the prefetch request early enough, such that when it is accessed it will already be stored in cache. For each instruction pointer (or group of them) BL∪E i) correlates in a timely way the cache lines that have been requested and ii) infers their timely delta when the cache lines have not been accessed yet.
Autor/es principal/es: Ros, Alberto
Facultad/Departamentos/Servicios: Facultades, Departamentos, Servicios y Escuelas::Departamentos de la UMU::Ingeniería y Tecnología de Computadores
Publicado en: The 1st ML-Based Data Prefetching Competition. ML for Computer Architecture and Systems
URI: https://drive.google.com/file/d/1lKWpaRGaW8nKRBDs8X1y-4AiMWLUAGWO/view
http://hdl.handle.net/10201/114664
Tipo de documento: info:eu-repo/semantics/article
Número páginas / Extensión: 4
Derechos: info:eu-repo/semantics/openAccess
Atribución 4.0 Internacional
Aparece en las colecciones:Artículos: Ingeniería y Tecnología de Computadores

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