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https://doi.org/10.1109/MICRO61859.2024.00067
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Título: | Chaining transactions for effective concurrency management in hardware transactional memory |
Fecha de publicación: | 3-dic-2024 |
Editorial: | IEEE Computer Society |
ISBN: | 979-8-3503-5057-9 |
Palabras clave: | Concurrent computing Context Microarchitecture Parallel programming Instruction sets Memory management Parallel processing Hardware Compelsity theory Proposals |
Resumen: | Hardware Transactional Memory (HTM) offers the opportunity to ease parallel programming. However, driven by hardware limitations, commercial implementations eschew the complexity involved in early sophisticated proposals from academia, and, among other things, opt for simple conflict resolution policies that inevitably increase transaction aborts. To increase thread level parallelism, previous works propose conflict resolution schemes that, instead of aborting, add a second level of speculation consisting in using not-yet-committed data from another transaction. This policy, which we refer to as requester-speculates, has not yet been considered in the context of the kind of best-effort HTM support provided by commercial processors. This work proposes CHAining TransactionS (CHATS), a simple yet effective realization of the requester-speculates con-flict resolution policy in which cyclic dependencies between transactions are avoided and the commit ordering respects the dependencies that transactions make once speculative values are communicated. The ultimate result is a best-effort HTM implementation that forces a partial order between transactions in a way that ensures effective utilization of forwarded data and that gets away from the complexity of previous proposals. Simulations using gem5 demonstrate the effectiveness of CHATS in both commercial-like setups and academic state-of-the-art best-effort systems (22% and 16% reduction in execution time, on average, respectively). These improvements are achieved by requiring less than 280 bytes of extra storage. |
Autor/es principal/es: | Nicolas Conesa, Víctor Titos Gil, Rubén Fernández Pascual, Ricardo Acacio, Manuel E. Ros Bardisa, Alberto |
Facultad/Departamentos/Servicios: | Facultades, Departamentos, Servicios y Escuelas::Departamentos de la UMU::Ingeniería y Tecnología de Computadores |
Forma parte de: | 57th IEEE/ACM International Symposium on Microarchitecture (MICRO), 2024, November 2-6, Austin, pp. 840-855 |
Versión del editor: | https://www.computer.org/csdl/proceedings-article/micro/2024/505700a840/22nis2QRdLi |
URI: | http://hdl.handle.net/10201/147625 |
DOI: | https://doi.org/10.1109/MICRO61859.2024.00067 |
Tipo de documento: | info:eu-repo/semantics/article |
Número páginas / Extensión: | 16 |
Derechos: | info:eu-repo/semantics/embargoedAccess |
Descripción: | © 2024 IEEE. This document is the Submitted version of a Published Work that appeared in final form in 57th IEEE/ACM International Symposium on Microarchitecture (MICRO). To access the final edited and published work see https://doi.org/10.1109/MICRO61859.2024.00067 |
Aparece en las colecciones: | Artículos: Ingeniería y Tecnología de Computadores |
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