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dc.contributor.authorNicolas Conesa, Víctor-
dc.contributor.authorTitos Gil, Rubén-
dc.contributor.authorFernández Pascual, Ricardo-
dc.contributor.authorAcacio, Manuel E.-
dc.contributor.authorRos Bardisa, Alberto-
dc.date.accessioned2024-12-18T11:05:50Z-
dc.date.available2024-12-18T11:05:50Z-
dc.date.issued2024-12-03-
dc.identifier.isbn979-8-3503-5057-9-
dc.identifier.urihttp://hdl.handle.net/10201/147625-
dc.description© 2024 IEEE. This document is the Submitted version of a Published Work that appeared in final form in 57th IEEE/ACM International Symposium on Microarchitecture (MICRO). To access the final edited and published work see https://doi.org/10.1109/MICRO61859.2024.00067es
dc.description.abstractHardware Transactional Memory (HTM) offers the opportunity to ease parallel programming. However, driven by hardware limitations, commercial implementations eschew the complexity involved in early sophisticated proposals from academia, and, among other things, opt for simple conflict resolution policies that inevitably increase transaction aborts. To increase thread level parallelism, previous works propose conflict resolution schemes that, instead of aborting, add a second level of speculation consisting in using not-yet-committed data from another transaction. This policy, which we refer to as requester-speculates, has not yet been considered in the context of the kind of best-effort HTM support provided by commercial processors. This work proposes CHAining TransactionS (CHATS), a simple yet effective realization of the requester-speculates con-flict resolution policy in which cyclic dependencies between transactions are avoided and the commit ordering respects the dependencies that transactions make once speculative values are communicated. The ultimate result is a best-effort HTM implementation that forces a partial order between transactions in a way that ensures effective utilization of forwarded data and that gets away from the complexity of previous proposals. Simulations using gem5 demonstrate the effectiveness of CHATS in both commercial-like setups and academic state-of-the-art best-effort systems (22% and 16% reduction in execution time, on average, respectively). These improvements are achieved by requiring less than 280 bytes of extra storage.es
dc.formatapplication/pdfes
dc.format.extent16es
dc.languageenges
dc.publisherIEEE Computer Societyes
dc.relationThis project has received funding from the European Research Council (ERC) under the European Union’s Horizon 2020 research and innovation program (ECHO, grant agreement No. 819134), from the Spanish Ministry of Science, Innovation and Universities (MCIN) MCIN/AEI/10.13039/501100011033/ and the “ERDF A way of making Europe”, EU (DAMAS, grant PID2022-136315OB-I00), and from the MCIN grant MCIN/AEI/10.13039/501100011033/ and the European Union NextGenerationEU/PRTR (HEEDA, grant TED2021- 130233B- C33).es
dc.relation.ispartof57th IEEE/ACM International Symposium on Microarchitecture (MICRO), 2024, November 2-6, Austin, pp. 840-855es
dc.rightsinfo:eu-repo/semantics/embargoedAccesses
dc.subjectConcurrent computinges
dc.subjectContextes
dc.subjectMicroarchitecturees
dc.subjectParallel programminges
dc.subjectInstruction setses
dc.subjectMemory managementes
dc.subjectParallel processinges
dc.subjectHardwarees
dc.subjectCompelsity theoryes
dc.subjectProposalses
dc.titleChaining transactions for effective concurrency management in hardware transactional memoryes
dc.typeinfo:eu-repo/semantics/articlees
dc.relation.publisherversionhttps://www.computer.org/csdl/proceedings-article/micro/2024/505700a840/22nis2QRdLies
dc.embargo.termsSI-
dc.identifier.doihttps://doi.org/10.1109/MICRO61859.2024.00067-
dc.contributor.departmentIngeniería y Tecnología de Computadores-
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