Por favor, use este identificador para citar o enlazar este ítem: 10.1109/TPDS.2021.3085210

Registro completo de metadatos
Campo DCValorLengua/Idioma
dc.contributor.authorTitos-Gil, Rubén-
dc.contributor.authorFernández-Pascual, Ricardo-
dc.contributor.authorAcacio Sánchez, Manuel Eugenio-
dc.contributor.authorRos, Alberto-
dc.contributor.otherFacultades, Departamentos, Servicios y Escuelas::Departamentos de la UMU::Ingeniería y Tecnología de Computadoreses
dc.date.accessioned2021-12-02T20:26:00Z-
dc.date.available2021-12-02T20:26:00Z-
dc.date.issued2022-01-
dc.identifier.citationIEEE Transactions on Parallel and Distributed Systems (TPDS), 33 (1)es
dc.identifier.issn1045-9219-
dc.identifier.urihttp://hdl.handle.net/10201/114665-
dc.description.abstractCommercial Hardware Transactional Memory (HTM) systems are best-effort designs that leverage the coherence substrate to detect conflicts eagerly. Resolving conflicts in favor of the requesting core is the simplest option for ensuring deadlock freedom, yet it is prone to livelocks. In this work, we propose and evaluate DeTraS (Delayed Transactional Stores), an HTM-aware store buffer design aimed at mitigating such livelocks. DeTraS takes advantage of the fact that modern commercial processors implement a large store buffer, and uses it to prevent transactional stores predicted to conflict from performing early in the transaction. By leveraging existing processor structures, we propose a simple design that improves the ability of requester-wins HTM systems to achieve forward progress in spite of high contention while side-stepping the performance penalty of falling back to mutual exclusion. With just over 50 extra bytes, DeTraS captures the advantages of lazy conflict management without the complexity brought into the coherence fabric by commit arbitration schemes nor the relaxation of the single-writer invariant of prior works. Through detailed simulations of a 16-core tiled CMP using gem5, we demonstrate that DeTraS brings reductions in average execution time of 25% when compared to an Intel RTM-like design.es
dc.formatapplication/pdfes
dc.format.extent13es
dc.languageenges
dc.relationEuropean Research Council (ERC) under the European Union s Horizon 2020 research and innovation programme (ECHO: Extending Coherence for Hardware-Driven Optimizations in Multicore Architectures, grant agreement No 819134, Consolidator Grant, 2018).es
dc.rightsinfo:eu-repo/semantics/openAccesses
dc.rightsAtribución 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/*
dc.subjectHardware Transactional Memoryes
dc.subjectStore bufferes
dc.subjectDelayes
dc.titleDeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memoryes
dc.typeinfo:eu-repo/semantics/articlees
dc.identifier.doi10.1109/TPDS.2021.3085210-
Aparece en las colecciones:Artículos: Ingeniería y Tecnología de Computadores

Ficheros en este ítem:
Fichero Descripción TamañoFormato 
rtitos-tpds22.pdf1,16 MBAdobe PDFVista previa
Visualizar/Abrir


Este ítem está sujeto a una licencia Creative Commons Licencia Creative Commons Creative Commons