Por favor, use este identificador para citar o enlazar este ítem:
10.1109/ISCA52012.2021.00017
Twittear
Registro completo de metadatos
Campo DC | Valor | Lengua/Idioma |
---|---|---|
dc.contributor.author | Ros, Alberto | - |
dc.contributor.author | Jimborean, Alexandra | - |
dc.contributor.other | Facultades, Departamentos, Servicios y Escuelas::Departamentos de la UMU::Ingeniería y Tecnología de Computadores | es |
dc.date.accessioned | 2021-12-02T19:49:01Z | - |
dc.date.available | 2021-12-02T19:49:01Z | - |
dc.date.issued | 2021-06 | - |
dc.identifier.uri | http://hdl.handle.net/10201/114663 | - |
dc.description.abstract | Prefetching instructions in the instruction cache is a fundamental technique for designing high-performance computers. There are three key properties to consider when designing an efficient and effective prefetcher: timeliness, coverage, and accuracy. Timeliness is essential, as bringing instructions too early increases the risk of the instructions being evicted from the cache before their use and requesting them too late can lead to the instructions arriving after they are demanded. Coverage is important to reduce the number of instruction cache misses and accuracy to ensure that the prefetcher does not pollute the cache or interacts negatively with the other hardware mechanisms. This paper presents the Entangling Prefetcher for Instructions that entangles instructions to maximize timeliness. The prefetcher works by finding which instruction should trigger the prefetch for a subsequent instruction, accounting for the latency of each cache miss. The prefetcher is carefully adjusted to account for both coverage and accuracy. Our evaluation shows that with 40KB of storage, Entangling can increase performance up to 23%, outperforming state-of-the-art prefetchers. | es |
dc.format | application/pdf | es |
dc.format.extent | 13 | es |
dc.language | eng | es |
dc.relation | European Research Council (ERC) under the European Union s Horizon 2020 research and innovation programme (ECHO: Extending Coherence for Hardware-Driven Optimizations in Multicore Architectures, grant agreement No 819134, Consolidator Grant, 2018). | es |
dc.relation.ispartof | 48th International Symposium on Computer Architecture (ISCA) | es |
dc.rights | info:eu-repo/semantics/openAccess | es |
dc.rights | Atribución 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by/4.0/ | * |
dc.subject | Instruction prefetching | es |
dc.subject | Caches | es |
dc.subject | Entangling | es |
dc.subject | Correlation | es |
dc.subject | Latency | es |
dc.title | A Cost-Effective Entangling Prefetcher for Instructions | es |
dc.type | info:eu-repo/semantics/article | es |
dc.identifier.doi | 10.1109/ISCA52012.2021.00017 | - |
Aparece en las colecciones: | Artículos: Ingeniería y Tecnología de Computadores |
Ficheros en este ítem:
Fichero | Descripción | Tamaño | Formato | |
---|---|---|---|---|
aros-isca21.pdf | 454,79 kB | Adobe PDF | Visualizar/Abrir |
Este ítem está sujeto a una licencia Creative Commons Licencia Creative Commons