Por favor, use este identificador para citar o enlazar este ítem: 10.1145/3466752.3480086

Título: ITSLF: Inter-Thread Store-to-Load Forwarding in Simultaneous Multithreading
Fecha de publicación: oct-2021
ISBN: 978-1-4503-8557-2
Palabras clave: Simultaneous Multithreading
Store-to-Load Forwarding
Multiple-Copy Atomicity
Resumen: In this paper, we argue that, for a class of fine-grain, synchronization-intensive, parallel workloads, it is advantageous to consolidate synchronization and communication as much as possible among the threads of simultaneous multithreading (SMT) cores. While, today, the shared L1 is the closest coherent level where synchronization and communication between SMT threads can take place, we observe that there is an even closer shared level, entirely inside a single core. This level comprises the load queues (LQ) and store queues (SQ) / store buffers (SB) of the SMT threads and to the best of our knowledge it has never been used as such. The reason is that if we allow communication of different SMT threads via their LQs and SQs/SBs, i.e., inter-thread store-to-load forwarding (ITSLF), we violate write atomicity with respect to the outside world, beyond the acceptable model of read-own-write-early multiple-copy atomicity (rMCA). The key insight of our work is that we can accelerate synchronization and communication among SMT threads with inter-thread store-to-load forwarding, without affecting the memory model—in particular without violating rMCA. We demonstrate how we can achieve this entirely through speculative interactions between LQs and SQs/SBs of different threads, while ensuring deadlock-free execution. Without changing the architectural model, the ISA, or the software, and without adding extra hardware in the form of a specialized accelerator, our insight enables a new design point for a standard architecture. We demonstrate that with ITSLF, workloads scale better on a single 8-way SMT core (with the resources of a single-threaded core) than on a baseline SMT (with or without optimizations), or on 8 single-threaded cores.
Autor/es principal/es: Feliú, Josué
Ros, Alberto
Acacio Sánchez, Manuel Eugenio
Kaxiras, Stefanos
Facultad/Departamentos/Servicios: Facultades, Departamentos, Servicios y Escuelas::Departamentos de la UMU::Ingeniería y Tecnología de Computadores
Publicado en: 54th International Symposium on Microarchitecture (MICRO)
URI: http://hdl.handle.net/10201/114645
DOI: 10.1145/3466752.3480086
Tipo de documento: info:eu-repo/semantics/article
Número páginas / Extensión: 13
Derechos: info:eu-repo/semantics/openAccess
Atribución 4.0 Internacional
Aparece en las colecciones:Artículos: Ingeniería y Tecnología de Computadores

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