Por favor, use este identificador para citar o enlazar este ítem: https://doi.org/10.1109/MICRO61859.2024.00017

Título: Secure prefetching for secure cache systems
Fecha de publicación: 3-dic-2024
Editorial: IEEE Computer Society
ISBN: 979-8-3503-5057-9
Palabras clave: Filters
Microarchitecture
Multicore processing
Prefetching
Information leakage
Turning
Hardware
Transient analysis
Proposals
Resumen: Transient execution attacks like Spectre and its vari-ants can cause information leakage through a cache hierarchy. There are two classes of techniques that mitigate speculative execution attacks: delay-based and invisible speculation. Invisible speculation-based techniques like GhostMinion are the high-performing yet secure techniques that mitigate all kinds of spec-ulative execution attacks. Similar to a cache system, hardware prefetchers can also cause speculative information leakage. To mitigate it, GhostMinion advocates on-commit prefetching on top of strictness ordering in the cache system. Our experiments show that the GhostMinion cache system interacts negatively with the hardware prefetchers leading to redundant traffic between different levels of cache. This traffic causes contention and increases the miss latency leading to performance loss. Next, we observe that on-commit prefetching enforced by GhostMinion leads to nerformance loss as it affects the prefetcher timeliness. We perform the first thorough analysis of the interaction between state-of-the-art prefetching techniques and the secure cache system. Based on this, we propose two microarchitectural solutions that ensure high performance while designing secure prefetchers on top of secure cache system. The first solution detects and filters redundant traffic when updating the cache hierarchy non-speculatively. The second solution ensures the timeliness of the prefetcher to compensate for the delayed triggering of prefetch requests at commit, resulting in a secure yet high-performing prefetcher. Overall, our enhancements are secure and provide synergistic interactions between hardware prefetchers and a secure cache system. Our experiments show that our filter consistently improves the performance of secure cache systems like GhostMinion in the presence of state-of-the-art prefetchers (by 1.9% for single-core and 19.0% for multi-core for the top-performing prefetcher). We see a synergistic behavior of the filter with our proposed secure prefetcher, which leads to a further increase in performance by 6.3% and 23.0% (over the top-performing prefetcher), for single-core and multi-core systems, respectively. Our enhancements are extremely lightweight incurring a storage overhead of 0.59 KB per core.
Autor/es principal/es: Nath, Sumon
Navarro Torres, Agustín
Ros Bardisa, Alberto
Panda, Biswabandan
Forma parte de: 57th IEEE/ACM International Symposium on Microarchitecture (MICRO), 2024, November 2-6, Austin, pp. 92-104
Versión del editor: https://www.computer.org/csdl/proceedings-article/micro/2024/505700a092/22niuf6jEJi
URI: http://hdl.handle.net/10201/147623
DOI: https://doi.org/10.1109/MICRO61859.2024.00017
Tipo de documento: info:eu-repo/semantics/article
Número páginas / Extensión: 13
Derechos: info:eu-repo/semantics/embargoedAccess
Descripción: © 2024 IEEE. This document is the Submitted version of a Published Work that appeared in final form in 57th IEEE/ACM International Symposium on Microarchitecture (MICRO). To access the final edited and published work see https://doi.org/10.1109/MICRO61859.2024.00017
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