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dc.contributor.authorShivdikar, Kaustubh-
dc.contributor.authorAgostini, Nicolas Bohm-
dc.contributor.authorJayaweera, Malith-
dc.contributor.authorJonatan, Gilbert-
dc.contributor.authorAbellán Miguel, José Luis-
dc.contributor.authorJoshi, Ajay-
dc.contributor.authorKim, John-
dc.contributor.authorKaeli, David-
dc.date.accessioned2024-04-26T11:28:09Z-
dc.date.available2024-04-26T11:28:09Z-
dc.date.issued2024-04-23-
dc.identifier.urihttp://hdl.handle.net/10201/141179-
dc.description©2024 ISCA. This manuscript version is made available under the CC-BY 4.0 license http://creativecommons.org/licenses/by/4.0/ This document is the Pre-print version published in arXiv. It will apear as a lecture in of ISCA 2024.es
dc.description.abstractGraph Neural Networks (GNNs) are emerging as a formidable tool for processing non-euclidean data across various domains, ranging from social network analysis to bioinformatics. Despite their effectiveness, their adoption has not been pervasive because of scalability challenges associated with large-scale graph datasets, particularly when leveraging message passing. They exhibit irregular sparsity patterns, resulting in unbalanced compute resource utilization. Prior accelerators investigating Gustavson’s technique adopted look-ahead buffers for prefetching data, aiming to prevent compute stalls. However, these solutions lead to inefficient use of the on-chip memory, leading to redundant data residing in cache. To tackle these challenges, we introduce NeuraChip, a novel GNN spatial accelerator based on Gustavson’s algorithm. NeuraChip decouples the multiplication and addition computations in sparse matrix multiplication. This separation allows for independent exploitation of their unique data dependencies, facilitating efficient resource allocation. We introduce a rolling eviction strategy to mitigate data idling in on-chip memory as well as address the prevalent issue of memory bloat in sparse graph computations. Furthermore, the compute resource load balancing is achieved through a dynamic reseeding hash-based mapping, ensuring uniform utilization of computing resources agnostic of sparsity patterns. Finally, we present NeuraSim, an open-source, cycle-accurate, multi-threaded, modular simulator for comprehensive performance analysis. Overall, NeuraChip presents a significant improvement, yielding an average speedup of 22.1× over Intel’s MKL, 17.1× over NVIDIA’s cuSPARSE, 16.7× over AMD’s hipSPARSE, and 1.5× over prior state of-the-art SpGEMM accelerator and 1.3× over GNN accelerator. The source code for our open-sourced simulator and performance visualizer is publicly accessible on GitHub.es
dc.formatapplication/pdfes
dc.format.extent15es
dc.languageenges
dc.publisherArXives
dc.relationInstitute for Experiential AI and the NSF IUCRC Center for Hardware and Embedded Systems Security and Trust (CHEST), NSF CNS 2312275, NSF CNS 2312276, and by Samsung Advanced Institute of Technology, Samsung Electronics Co., Ltd. Additionally, we acknowl edge the financial assistance from grant RYC2021-031966-I funded by MCIN/AEI/10.13039/501100011033 and the “European Union NextGenerationEU/PRTR.”, and grant PID2022-136315OB-I00 funded by MCIN/AEI/10.13039/501100011033/ and by “ERDF A way of making Europe”, EU.es
dc.relation.ispartofISCA 2024 : International Symposium on Computer Architecture, Argentinaes
dc.rightsinfo:eu-repo/semantics/openAccesses
dc.rightsAtribución 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/*
dc.subjectGraph Neural Networks (GNN)es
dc.subjectDecoupled Computationses
dc.subjectSpatial Acceleratorses
dc.subjectSparse Matrix Multiplication (SpGEMM)es
dc.subjectOn-chip Memoryes
dc.subjectHardware-software co-designes
dc.subject.otherCDU::6 - Ciencias aplicadas::62 - Ingeniería. Tecnologíaes
dc.titleNeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial Acceleratores
dc.typeinfo:eu-repo/semantics/articlees
dc.typeinfo:eu-repo/semantics/lecturees
dc.relation.publisherversionhttps://arxiv.org/abs/2404.15510es
dc.contributor.departmentDepartamento de Ingeniería y Tecnología de Computadores-
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