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Título: POAS: a framework for exploiting accelerator level parallelism in heterogeneous environments
Fecha de publicación: 25-mar-2024
Editorial: Springer
Cita bibliográfica: The Journal of Supercomputing, 2024
ISSN: Print: 0920-8542
Electrónic: 1573-0484
Palabras clave: High-performance computing
Heterogeneous computing
Accelerator level parallelism
Scheduling
Co-execution
Resumen: In the era of heterogeneous computing, a new paradigm called accelerator level parallelism (ALP) has emerged. In ALP, accelerators are used concurrently to provide unprecedented levels of performance and energy efficiency. To reach that there are many problems to be solved, one of the most challenging being co-execution. In this paper, we present a new scheduling framework called POAS, a general method for providing co-execution to applications. Our proposal consists of four steps: predict, optimize, adapt and schedule. With POAS, an unseen application can be executed concurrently in ALP with little effort. We evaluate POAS on a heterogeneous environment consisting of CPUs, GPUs (CUDA cores), and XPUs (Tensor cores) on two different fields, namely linear algebra (matrix multiplication benchmark) and deep learning (convolution benchmark). Our experiments prove that POAS provides excellent performance and completes the tasks within a time very close to the optimal time for the hardware and applications used, with a negligible execution time overhead. Moreover, the POAS predictor performed exceptionally well, achieving very low RMSE values for both use cases. Therefore, POAS can be a valuable tool for fully exploiting ALP and improving overall performance over offloading in heterogeneous settings.
Autor/es principal/es: Martínez Sánchez, Pablo Antonio
Bernabé García, Gregorio
García Carrasco, José Manuel
URI: http://hdl.handle.net/10201/140581
DOI: https://doi.org/10.1007/s11227-024-06008-w
Tipo de documento: info:eu-repo/semantics/article
Número páginas / Extensión: 28
Derechos: info:eu-repo/semantics/embargoedAccess
Descripción: ©2024. This document is the Accepted, version of a Published Work that appeared in final form in The Journal of Supercomputing. To access the final edited and published work see https://doi.org/10.1007/s11227-024-06008-w
Aparece en las colecciones:Artículos: Ingeniería y Tecnología de Computadores

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