Por favor, use este identificador para citar o enlazar este ítem:
https://doi.org/10.1109/HPCA57654.2024.00045
Twittear
Registro completo de metadatos
Campo DC | Valor | Lengua/Idioma |
---|---|---|
dc.contributor.author | Kim, Sebastian S. | - |
dc.contributor.author | Ros, Alberto | - |
dc.contributor.other | Facultades, Departamentos, Servicios y Escuelas::Departamentos de la UMU::Ingeniería de la Información y las Comunicaciones | es |
dc.date.accessioned | 2024-03-20T12:30:44Z | - |
dc.date.available | 2024-03-20T12:30:44Z | - |
dc.date.issued | 2024-03 | - |
dc.identifier.issn | 2378-203X | - |
dc.identifier.uri | http://hdl.handle.net/10201/140322 | - |
dc.description | ©2024. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/ This document is the Accepted version of a Published Work that appeared in final form in IEEE Computer Society. To access the final edited and published work see https://doi.org/10.1109/HPCA57654.2024.00045 | es |
dc.description.abstract | Memory dependence prediction is a fundamental technique to increase instruction- and memory-level parallelism in out-of-order processors, which are crucial for high performance. However, over the years, the performance gap of state-of-the-art memory dependence predictors with respect to an ideal predictor has grown due to the increase of the pipeline width, reaching up to 6% for modern architectures. State-of-the-art predictors brace context sensitivity, however, not-well-adjusted history lengths lead to loss of accuracy and high storage requirements. This work proposes PHAST, a novel context-sensitive memory dependence predictor that identifies for each load the minimum history length necessary to provide precise predictions. Our key observation is that for each load, it suffices to identify the youngest conflicting store and the path between them. This observation is proven empirically using an unlimited budget version of PHAST, which performs close to an ideal predictor with a 0.47% gap. Through cycle-accurate simulation of the SPEC CPU 2017 suite, we show that a 14.5KB implementation of PHAST falls 1.50% behind an ideal predictor. Compared to the top-performing state-of-the-art predictors, PHAST achieves average speedups of 5.05% (up to 39.7%), 1.29% (up to 22.0%), and 3.04% (up to 38.2%) with respect to an 18.5KB StoreSets, a 19KB NoSQ, and a 38.6 MDP-TAGE, respectively. This stems from a considerable misprediction reduction, ranging between 62.5% and 70.0%, on average. | es |
dc.format | application/pdf | es |
dc.format.extent | 13 | es |
dc.language | eng | es |
dc.relation | This project has received funding from the European Research Council (ERC) under the European Union’s Horizon 2020 research and innovation program (grant agreement No 819134), from the CIN/AEI/10.13039/501100011033/ and the “ERDF A way of making Europe”, EU (grant PID2022-136315OB-I00), and from the MCIN/AEI/10.13039/501100011033/ and the European Union NextGenerationEU/PRTR (grant TED2021-130233B C33). Sebastian S. Kim is a PhD student funded by the Fundacion S ´ eneca, Regi ´ on of Murcia (21456/FPI/20). | es |
dc.relation.ispartof | 2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA) | es |
dc.rights | info:eu-repo/semantics/openAccess | es |
dc.rights.uri | http://creativecommons.org/licenses/by/4.0/ | * |
dc.title | Effective Context-Sensitive Memory Dependence Prediction | es |
dc.type | info:eu-repo/semantics/article | es |
dc.identifier.doi | https://doi.org/10.1109/HPCA57654.2024.00045 | - |
Aparece en las colecciones: | Artículos: Ingeniería y Tecnología de Computadores |
Ficheros en este ítem:
Fichero | Descripción | Tamaño | Formato | |
---|---|---|---|---|
sskim-hpca24.pdf | 618,77 kB | Adobe PDF | Visualizar/Abrir |
Este ítem está sujeto a una licencia Creative Commons Licencia Creative Commons