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Campo DC | Valor | Lengua/Idioma |
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dc.contributor.author | Jimborean, Alexandra | - |
dc.contributor.author | Koukos, Konstantinos | - |
dc.contributor.author | Spiliopoulos, Vasileios | - |
dc.contributor.author | Black-Schaffer, David | - |
dc.contributor.author | Kasiras, Stefanos | - |
dc.date.accessioned | 2024-02-01T08:35:30Z | - |
dc.date.available | 2024-02-01T08:35:30Z | - |
dc.date.created | 2014 | - |
dc.identifier.citation | IEEE/ACM Transactions on Networking, February 15-19 2014: 262 - 272 | es |
dc.identifier.issn | 1558-2566 | - |
dc.identifier.uri | http://hdl.handle.net/10201/138368 | - |
dc.description.abstract | Traditional compiler approaches to optimize power effi-ciency aim to adjust voltage and frequency at runtime tomatch the code characteristics to the hardware (e.g., run-ning memory-bound phases at a lower frequency). However,such approaches are constrained by three factors: (i) voltage-frequency transitions are too slow to be applied at instructiongranularity, (ii) larger code regions are seldom unequivocallymemory- or compute-bound, and, (iii) the available voltagescaling range for future technologies is rapidly shrinking.These factors necessitate new approaches to address power-efficiency at the code-generation level. This paper proposesone such approach to automatically generate power-efficientcode using a decoupled access/execute (DAE) model.In DAE a program is split into tasks, where each task con-sists of two sufficiently coarse-grained phases to enable ef-fective Dynamic Voltage Frequency Scaling (DVFS): (i) theaccess-phase for data prefetch (heavily memory-bound), and(ii) theexecute-phase that performs the actual computation(heavily compute-bound). Our contribution is to provide acompiler methodology to automatically generate the access-phases for a task-based programming system. Our approachis capable of handling both affine (through a polyhedral anal-ysis) and non-affine codes (through optimized task skele-tons). Our evaluation shows that the automatically gener-ated versions improve EDP by 25% on average comparedto a coupled execution, without any performance degrada-tion, and surpasses the EDP savings of the correspondinghand-crafted tasks by 5% | es |
dc.format | application/pdf | es |
dc.format.extent | 11 | es |
dc.language | eng | es |
dc.publisher | IEEE/ACM | es |
dc.relation | We thank Vincent Loechner for his insights on the polyhedral model and his valuable help. This work is supported, in part, by the Swedish Research Council UPMARC Linnaeus Centre and the EU Project: LPGPU FP7-ICT-288653. | es |
dc.relation.ispartof | 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization 2014 | es |
dc.rights | info:eu-repo/semantics/embargoedAccess | es |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.subject | Compiler Optimizations | es |
dc.subject | Polyhedral Model | es |
dc.subject | Task-Based Execution | es |
dc.subject | Execution | es |
dc.subject | Performance | es |
dc.subject | Energy | es |
dc.subject | DVFS | es |
dc.title | Fix the code. Don’t tweak the hardware: A newcompiler approach to Voltage-Frequency scaling | es |
dc.type | info:eu-repo/semantics/article | es |
dc.relation.publisherversion | https://dl.acm.org/citation.cfm?id=2544161 | es |
dc.embargo.terms | Si | - |
dc.identifier.doi | http://dx.doi.org/10.1145/2544137.2544161 | - |
dc.contributor.department | Departamento de Ingeniería y Tecnología de Computadores | - |
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